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Cao

Yu Cao

  • Associate Professor
School of Computing, Informatics, and Decision Systems Engineering
  • Computer Science and Engineering
  • Electrical Engineering
  • Bio
  • Expertise
  • Education
  • Honors & Distinctions
  • Selected Publications

Kevin Cao joined the ASU faculty in 2004. He received a PhD in electrical engineering in 2002 and an MA in biophysics in 1999 from the University of California, Berkeley, and conducted his post-doctoral research at the Berkeley Wireless Research Center.  He has published more than 120 articles and co-authored one book on nano-CMOS physical and circuit design. He has served on the technical program committee of many conferences and is a member of the IEEE EDS Compact Modeling Technical Committee.

Physical modeling of nanoscale technologies, design solutions for variability and reliability, and reliable integration of post-silicon technologies.

Ph.D. Electrical Engineering
University of California - Berkeley 2002

Promotion and Tenure Faculty Exemplar, Arizona State University, 2009; Distinguished Lecturer of the IEEE Circuits and Systems Society, 2009; Chunhui Award for Outstanding Oversea Chinese Scholars, China, 2008; Best Paper Award at the International Low-Power Electronics and Design, 2007; IBM Faculty Award, 2007 and 2006; NSF Faculty Early Career Development (CAREER) Award, 2006; Best Paper Award at the International Symposium on Quality Electronic Design, 2004; Beatrice Winner Award, International Solid-State Circuits Conference, 2000; Biophysics Graduate Program Fellowship at the University of California, Berkeley, 1997-98; UC Regents Fellowship at University of California, Santa Cruz, 1996-97.

D. Acharyya, K. Agarwal, Y. Cao, F. Liu, S. R. Nassif, K. Nowka and W. Zhao, “Rigorous extraction of process variations for 65nm CMOS design,” IEEE Transactions on Semiconductor Manufacturing, vol. 22, no. 1, 196-203, February 2009.

T. Austin, V. Bertacco, Y. Cao and S. Mahlke, “Reliable systems on unreliable fabrics,” IEEE Design & Test of Computers, vol. 25, no. 4, 322-332, July-August, 2008.

B. H. Calhoun, Y. Cao, X. Li, K. Mai, L. T. Pileggi, R. A. Rutenbar, and K. L. Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS,” Proceedings of the IEEE, vol. 96, no. 2, 343-365, February 2008.

W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S. Krishnan, Y. Cao, “Compact modeling and simulation of circuit reliability for 65nm CMOS technology,” IEEE Transactions on Device and Materials Reliability, vol. 7, no. 4, 509-517, December 2007.

W. Zhao and Y. Cao, “Predictive technology model for nano-CMOS design exploration,” ACM Journal on Emerging Technologies in Computing Systems, vol. 3, no. 1, 1-17, April 2007.

A. Balijepalli, S. Sinha, Y. Cao, “Compact Modeling of Carbon Nanotube Transistor for Early Stage Process-design Exploration,” International Symposium on Low Power Electronics and Design, 2-7, 2007.